Conference Publication
2017-12-15
2019
[ASP-DAC'19].Jianfei Wang, Li Jiang, Jing Ke, Xiaoyao Liang and Naifeng Jing*, “A Sharing-Aware L1.5D Cache for Data Reuse in GPGPUs”,accepted by Asia and South Pacific Design Automation Conference, pp.1-6, 21-24, Jan.2019 (CCF-C)
2018
[FPGA’18]. Haiyue Song, Xiang Song, Tianjian Li, Naifeng Jing, Xiaoyao Liang and Li Jiang*, “A FPGA friendly approximate computing framework with hybrid Neural networks”, accepted by ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018 (Poster) (CCF-B)
[DATE’18]. Houxiang Ji, Linghao Song, Li Jiang, Hai (Halen) Li and Yiran Chen, “RECOM: An Efficient Resistive Accelerator for Compressed Deep Neural Networks”, accepted by ACM/IEEE Design Automation and Test in Europe Conference, 2018 (CCF-B)
[DATE’18]. Pu Pang, Yixun Zhang, Tianjian Li, Sung Kyu Lim, Quan Chen, Xiaoyao Liang and Li Jiang*, “In-growth Test for Monolithic 3D SRAM”, accepted by ACM/IEEE Design Automation and Test in Europe Conference, 2018 (CCF-B)
2017
[DAC’17]. Chengwen Xu, Xiangyu Wu, Wenqi Yin, Qiang Xu, Naifeng Jing, Xiaoyao Liang and Li Jiang*, “On Quality Trade-off Control for Approximate Computing using Iterative Training”, ACM/IEEE Design Automation Conference, Article 52, 2017 (CCF-B)
[DAC’17]. Tianjian Li, Xiangyu Bi, Naifeng Jing, Xiaoyao Liang and Li Jiang*, “Sneak-path based Test and Diagnosis for 1R RRAM Crossbar using Voltage Bias Technique”, ACM/IEEE Design Automation Conference, Article 38, 2017 (CCF-B)
[DATE’17]. Lerong Chen, Jiawen Li, Yiran Chen, Qiuping Deng, Jiyuan Shen, Xiaoyao Liang and Li Jiang*, “Accelerator-friendly neural-network training: Learning variations and defects in RRAM crossbar”, ACM/IEEE Design Automation & Test in Europe Conference and Exhibition, pp. 19 - 24, April. 2017 (CCF-B)
[DATE’17]. Tianjian Li, Yan Han, Xiaoyao Liang, Hsien-Hsin S. Lee and Li Jiang*, “Fault Clustering Technique for 3D Memory BISR”, ACM/IEEE Design Automation & Test in Europe Conference and Exhibition, pp. 560 - 565, April. 2017 (CCF-B)
2016
[ISPDC’16].Fengfeng Fan, Jianfei Wang, Li Jiang, Xiaoyao Liang and Naifeng Jing, “Applying Victim Cache in High Performance GPGPU Computing”, International Symposium on Parallel and Distributed Computing. (Best Paper Award)
[ISCA’16].Chao Li, Zhenhua Wang, Xiaofeng Hou, Haopeng Chen, Xiaoyao Liang, and Minyi Guo, “Power Attack Defense: Securing Battery-Backed Data Centers”, 43rd ACM/IEEE Int. Symp. on Computer Architecture.
[ITC’16]. Tianjian Li, Li Jiang*, Xiaoyao Liang, Qiang Xu and Krishnendu Chakrabarty, “Defect Tolerance for CNFET-based SRAMs”, IEEE International Test Conference, paper 4.1, Nov. 2016 (CCF-B)
[ICCD’16]. Tianjian Li, Li Jiang*, Naifeng Jing, Nam Sung Kim and Xiaoyao Liang, “CNFET-Based High Throughput Register File Architecture”, IEEE International Conference on Computer Design, pp. 662 - 669, Oct. 2016 (CCF-B)
[MICRO’16]. Naifeng Jing, Jianfei Wang, Fengfeng Fan, Wenkang Yu, Li Jiang, Chao Li and Xiaoyao Liang, “Cache-Emulated Register File: An Integrated On-Chip Memory Architecture for High Performance GPGPUs”, ACM/IEEE International Symposium on Microarchitecture, pp. 1 - 12, 2016 (CCF-A)
2015
[ICPP’15].Weichao Tang, Yu Wang, Haopeng Liu, Tao Zhang, Chao Li, Xiaoyao Liang, “Exploring Hardware Profile-Guided Green Datacenter Scheduling,” International Conference on Parallel Processing.
[ISLPED’15].Xiangyu Wu, Yuanfang Xia, Naifeng Jing, Xiaoyao Liang, “CGSharing: Efficient Content Sharing in GPU-Based Cloud Gaming,” International Symposium on Low Power Electronics and Design.
[ISCA’15].Chao Li, Longjun Liu, Yang Hu, Juncheng Gu, Mingcong Song, Xiaoyao Liang, Jingling Yuan, Tao Li, “Towards Sustainable In-Situ Server Systems in the Big Data Era, ” International Symposium on Computer Architecture.
[ICCD’15]. Li Jiang, Xiangwei Huang, Hongfeng Xie, Qiang Xu, Chao Li, Xiaoyao Liang and Huiyun Li, “A Novel TSV Probing Technique with Adhesive Test Interposer”, International Conference on Computer Design, pp. 597 - 604, Oct. 2015 (CCF-B)
[ITC’15]. Li Jiang, Pu Pang, Naifeng Jing, Sung Kyu Lim, Xiaoyao Liang and Qiang Xu, “On Diagnosable and Tunable 3D Clock Network Design for Lifetime Reliability Enhancement”, International Test Conference, paper 17.1, Oct. 2015 (CCF-B)
[ITC’15]. Li Jiang, and Qiang Xu, “Yield and Reliability Enhancement for 3D ICs”, International Test Conference, paper DDC.3, Oct. 2015 (CCF-B)
[NOCS’15]. Li Jiang, and Qiang Xu, “Fault-tolerant 3D-SoCs: Recent advances and challenges”, Network-on-chip Symposium, pp. 1 - 8, Sep. 2015 (CCF-C)
[IEEE-SOCC’15]. Tianjian Li, Hao Chen, Weikang Qian, Xiaoyao Liang, and Li Jiang*, “On Microarchitectural Modeling for CNFET-based Circuits”, IEEE System On Chip Conference, Sep. 2015
[IEEE-SOCC’15]. Chen Wang, Li Jiang*, Tianjian Li, Xiaoyao Liang, Weikang Qian, “Timing-Driven Placement for Carbon Nanotube Circuits”, IEEE System On Chip Conference, Sep. 2015
[ISLPED’15]. Naifeng Jing, Shuang Chen, Shunning Jiang, Li Jiang, Chao Li, Xiaoyao Liang, “Bank Stealing for Conflict Mitigation in GPGPU Register File”, International Symposium on Low Power Electronics and Design, pp. 55 - 60, July 2015 (CCF-B)
[ICS’15]. Yiqing Hua, Chao Li, Weichao Tang, Li Jiang, Xiaoyao Liang, “Building Fuel Powered Supercomputing Data Center at Low Cost”, International Conference on Supercomputing, pp. 241 - 250, June 2015 (CCF-B)
[DAC’15] Feng Xie, Xiaoyao Liang, Qiang Xu, Krishnendu Chakrabarty, Naifeng Jing and Li Jiang*, “Jump Test for Metallic CNTs in CNFET-Based SRAM”, Design Automation Conference, pp. 1 - 6, 2015 (CCF-B)
2014
[ICPADS’14] Xiaodong Meng, Chentao Wu, Minyi Guo, Jie Li, Xiaoyao Liang, Long Zheng, Bin Yao, "HFA: A Hint Frequency-based Approach to Enhance the I/O Performance of Multi-level Cache Storage Systems," 20th IEEE International Conference on Parallel and Distributed Systems.
[ICCD’14]Tao Zhang, Xiaoyao Liang, "Dynamic Front-End Sharing in Graphic Processing Units," International Conference on Computer Design.
[BigComp’14]Mingyang Yang, Bin Yao, Yingkai Li, Jinsong Bao, Yao Shen, Jingyu Zhou, Chentao Wu, Feilong Tang, Minyi Guo, Xiaoyao Liang, Li Li, “Spatio-Textual k Nearest Neighbor Joins using MapReduce,” International Conference on Big Data and Smart Computing.
[BigComp’14]Bin Yao, Yue Yin, Jinsong Bao, Yao Shen, Jingyu Zhou, Chentao Wu, Feilong Tang, Minyi Guo, Xiaoyao Liang, Li Li, “An Index Framework for Distributed Data Warehouse,” International Conference on Big Data and Smart Computing.
2009-2013
[ISLPED’13]Naifeng Jing, Haopeng Liu, Yao Lu, Xiaoyao Liang, “Compiler Assisted Dynamic Register File in GPGPU,” International Symposium on Low Power Electronics and Design.
[ISCA’13]Naifeng Jing, Yao Shen, Yao Lu, Shrikanth Ganapathy, Zhigang Mao, Minyi Guo, Ramon Canal, Xiaoyao Liang, “An Energy-Efficient and Scalable eDRAM-Based Register File Architecture for GPGPU”, International Symposium on Computer Architecture.
[ASP-DAC’13] Zelong Sun, Li Jiang, Qiang Xu, Zhaobo Zhang, Zhiyuan Wang and Xinli Gu, “On Test Syndrome Merging for Reasoning Based Board-Level Functional Fault Diagnosis”, Proc. IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 737 - 742, 2013 (CCF-C)
[ITC’13] Zelong Sun, Li Jiang, Qiang Xu, Zhaobo Zhang, Zhiyuan Wang and Xinli Gu, “AgentDiag: An Agent-Assisted Diagnostic Framework for Board-Level Functional Failures”, IEEE International Test Conference (ITC), paper 11.2, 2013 (CCF-C)
[DAC’13] Li Jiang, Qiang Xu, Feng Ye, Krishnendu Chakrabarty and Bill Eklow, “On Effective and Efficient In-Field TSV Repair for Stacked 3D ICs”, Proc. ACM/IEEE Design Automation Conference, pp. 1 - 6, 2013 (CCF-B)
[HPCA’12] Guihai Yan, Yingmin Li, Yinhe Han, Xiaowei Li, Minyi Guo, Xiaoyao liang, “AgileRegulator: A Hybrid Voltage Regulator Scheme Redeeming Dark Silicon for Power Efficiency in a Multicore Architecture”, International Symposium on High Performance Computer Architecture.
[DATE’12] Li Jiang, Qiang Xu and Bill Eklow, “On Effective TSV Repair for 3D-Stacked ICs”, Proc. Design, Automation & Test in Europe Conference & Exhibition, pp. 793 - 798, 2012 (CCF-B)
[ASP-DAC’12] Qiang Xu, Li Jiang, Huiyun Li and Bill Eklow, “Yield Enhancement for 3D-Stacked ICs: Recent Advances and Challenges”, Proc. IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 731 - 737, 2012 (Invited) (CCF-C)
[ISCA’10]GuihaiYan, Xiaoyao Liang, Yinhe Han, Xiaowei Li, “Leveraging the Core-Level Driven Complementary Effects of PVT Variations to Reduce Timing Emergencies in Multi-Core Processors,” International Symposium on Computer Architecture.
[ICCAD’10] Li Jiang, Rong Ye and Qiang Xu, “Yield Enhancement for 3D-Stacked Memory by Redundancy Sharing across Dies”, Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 230 - 234, 2010 (Nominated for Best Paper Award) (CCF-B)
[ITC’10] Li Jiang, Yuxi Liu, Lian Duan, Yuan Xie and Qiang Xu, “Modeling TSV Open Defects in 3D-Stacked DRAM”, Proc. IEEE International Test Conference, pp. 1 - 9, 2010 (CCF-B)
[ICCD’09] Kristen Lovin, Benjamin Lee, Xiaoyao Liang, Gu-Yeon Wei, David Brooks, “Empirical Performance Models for 3T1D Memories,” International Conference on Computer Design.
[ICCD’09] Xiaoyao Liang, Benjamin Lee, David Brooks, Gu-Yeon Wei, “Design and Test Strategies for Microarchitectural Post-Fabrication Tuning,” International Conference on Computer Design.
[ISLPED’09] Guihai Yan, Yinhe Han, Hui Liu, Xiaoyao Liang, Xiaowei Li, “MicroFix: Exploiting Path-Grained Timing Adaptability for Improving Power-Performance Efficiency,” International Symposium on Low Power Electronics and Design.
[ICCAD’09] Li Jiang, Qiang Xu, Krishnendu Chakrabarty and T. M. Mak, “Layout-Driven Test-Architecture Design and Optimization for 3D SoCs under Pre-Bond Test-Pin-Count Constraint”, Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 191 - 196, 2009 (CCF-B)
[DATE’09] Li Jiang, Lin Huang and Qiang Xu, “Test Architecture Design and Optimization for Three-Dimensional SoCs”, Proc. IEEE/ACM Design, Automation, & Test in Europe, pp. 220 - 225, 2009 (CCF-B)
2004-2008
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks, “DRAM-based On-Chip Cache Architectures to Combat Process Variations,” Intel 2008 European Research and Innovation Conference, September 2008.
[ISLPED’08] Gu-Yeon Wei, David Brooks, A. Durlov Khan, Xiaoyao Liang, “Instruction-Driven Clock Scheduling with Glitch Mitigation,” International Symposium on Low Power Electronics and Design.
[ISCA’08]Xiaoyao Liang, Gu-Yeon Wei, David Brooks, “ReVIVaL: A Variation Tolerant Architecture Using Voltage Interpolation and Variable Latency,” International Symposium on Computer Architecture.
[ISSCC’08]Xiaoyao Liang, Gu-Yeon Wei, David Brooks, “A Process-Variation-Tolerant Floating-Point Unit with Voltage Interpolation and Variable Latency,” IEEE International Solid State Circuit Conference.
[MICRO’07]Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks, “Process Variation Tolerant 3T1D-based Cache Architectures,” 40th International Symposium on Microarchitecture.
[ICCAD’07]Xiaoyao Liang, Kerem Turgay, David Brooks, “Architectural Power Models for SRAM and CAM Structures Based on Hybrid Analytical/Empirical Techniques,” International Conference on Computer Aided Design.
[ASGI’07]Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks, “Process Variation Tolerant Register Files Based on Dynamic Memories,” Workshop on Architectural Support for Gigascale Integration.
[MICRO’06]Xiaoyao Liang, David Brooks, “Mitigating the Impact of Process Variations on CPU Register File and Execution Units,” 39th International Symposium on Microarchitecture.
[ICCAD’06]Xiaoyao Liang, David Brooks, “Microarchitecture Parameter Selection to Optimize System Performance under Process Variation,” International Conference on Computer Aided Design.
Mark Hempstead, Xiaoyao Liang, Patrick Mauro, Gu-Yeon Wei, David Brooks, “Design and Implementation of An Ultra Low Power System Architecture for Wireless Sensor Network Applications,” SRC Techcon, SoC Design Contest - Phase II, 1st place, October 2006.
[ASGI’06]Xiaoyao Liang, David Brooks, “Latency Adaptation for Multi-ported Register Files to Mitigate the Impact of Process Variations,” Workshop on Architectural Support for Gigascale Integration.
Xiaoyao Liang, David Brooks, “Highly Accurate Power Modeling Method for SRAM Structures with Simple Circuit Simulation,” The Second Watson Conference on Interaction between Architecture, Circuits, and Compilers (p=ac2), September 2005.
[ISCAS’05]Xiaoyao Liang, Akshay Athalye, Sangjing Hong, “Equalizing Execution Path for Processing Speed Determination in Block Level Pipelining,” IEEE International Symposium on Circuits and Systems.
[ISCAS’05]Xiaoyao Liang, Akshay Athalye, Sangjing Hong, “Dynamic Corse Grain Dataflow Reconfiguration Technique for Real-Time System Design,” IEEE International Symposium on Circuits and Systems.
Mark Hempstead, Xiaoyao Liang, Patrick Mauro, Gu-Yeon Wei, David Brooks, “Design and Implementation of An Ultra Low Power System Architecture for Wireless Sensor Network Applications,” SRC Techcon, SoC Design Contest - Phase I, 2nd place, October 2005.
[RTSS’04]Yulei Weng, Sankalp Kallakuri, Xiaoyao Liang, Alex Doboli, et. al, “Dynamic Architecture Adaptation to Improve Scalability of Sensor Networks: A Case Study for a Smart Sensor for Face Recognition,” 25th IEEE International Real-Time Systems Symposium.
[SIPS’04]Sangjin Hong, Xiaoyao Liang, Petar Djuric, “Reconfigurable Particle Filter Design Using Dataflow Structure Translation”, IEEE Workshop on Signal Processing Systems.
[ICSP’04]Sangjin Hong, Xiaoyao Liang, Miodrag Bolic, Petar Djuric, “Data Centric SIR Particle Filter Design Using Buffer-level Pipelining”, 7th International Conference on Signal Processing.
[ICSP’04]Sangjin Hong, Xiaoyao Liang, Miodrag Bolic, Petar Djuric, “Design and Synchronization of Gaussian Particle Filter Using Distributed Controller Scheme”, 7th International Conference on Signal Processing.
[ICSP’04]Sangjin Hong, Magesh Sadasivam, Xiaoyao Liang, “Post-Generation of Overall Execution Controller for Data Centric Signal Processing Algorithms,” 7th International Conference on Signal Processing.